Advances in integrated circuit technology have enabled the development of complex “system-on-a-chip” ICs for a variety of applications such as wireless communications and digital cameras. Such applications are embodied in portable electronic devices for which low power and small circuit area are important design factors. Low power and low voltage circuits are needed to decrease battery power requirements, which can allow for designs that use fewer or smaller batteries, which in turn decreases device size, weight, and operating temperature.
Such devices, however, receive analog input signals that are typically converted to digital signals. Various conventional cyclic (algorithmic) A/D converters that achieve low power operation and high resolution in a small area are known. For example, U.S. Pat. No. 6,535,157, herein incorporated by reference, discloses a cyclic RSD A/D converter having a single RSD stage followed by a digital logic section that performs synchronization and correction functions.
Referring to FIG. 1, a block diagram of a cyclic RSD A/D converter 100, such as the one disclosed in U.S. Pat. No. 6,535,157, is shown. The A/D converter 100 includes an analog section having a single RSD stage 110 followed by digital section 120 having an alignment and synchronization block 130 and a correction block 140. An analog input signal (e.g., voltage) is input to the first RSD stage 110 by way of a first switch 112. The RSD stage 110 provides a digital output signal to the digital section 120. The RSD stage 110 also generates a residual voltage signal (VR), which is fed back by way of the first switch 112. The first switch 112 is closed for the first clock cycle, in which the analog input signal is received, and then opened for the remaining number of clock cycles that it takes to complete converting the analog signal to a digital signal. The feedback loop of the RSD stage 110 is directly connected from the RSD stage output to the first switch 112. The number of clock cycles to complete the A/D conversion depends on the number of bits in the digital output signal. The digital bits output from the RSD stage 110 are provided to the digital section 120, where they are aligned, synchronized, and combined to provide a standard format binary output code.
While the single stage solution of U.S. Pat. No. 6,535,157 provides a low power, high resolution, and high speed A/D converter 100, there is still a need for a single stage A/D converter that uses less power and has a decreased silicon area. Embodiments of the invention address these and other disadvantages of the related art.